1. Field of the Invention
The disclosed embodiments of the present invention relate to an interface protocol of a memory device, and more particularly, to an asynchronous control method of a memory device, and a related memory device and a memory system.
2. Description of the Prior Art
A nowadays high performance integrated circuit (IC) utilizes a synchronous operation to achieve a high data access frequency. A synchronous memory operates with a latency which is a predetermined number of clock cycles between the application of a read/write address and the access of corresponding data, wherein the application of other read/write address(es) is allowed before the access of the corresponding data is completed. This increases the data access frequency. In contrast, data access of an asynchronous memory is defined by the application of a read/write address and the access of data, wherein a next read/write address is not applied until the current data access is completed. In other words, the asynchronous memory cannot have a high data access frequency. However, peripheral circuitry of a conventional high performance memory has a large size, causing side effects such as a great increase in area/cost of a memory die, and high power consumption.
Thus, there is a need for a novel memory architecture and a transmission interface protocol. Hence, optimization of bandwidth and power consumption can be considered from a memory system viewpoint, and an overall cost of a memory system can be reduced accordingly.